Modern integrated circuits are formed on the surfaces of semiconductor substrates, which are mostly silicon substrates. Semiconductor devices are isolated from each other by isolation structures formed close to the surface of the respective semiconductor substrates. The isolation structures include field oxides and shallow trench isolation (STI) regions.
Field oxides are often formed using local oxidation of silicon (LOCOS). A typical formation process includes blanket forming a mask layer on a silicon substrate and then patterning the mask layer to expose certain areas of the underlying silicon substrate. A thermal oxidation is then performed in an oxygen-containing environment to oxidize the exposed portions of the silicon substrate. The mask layer is then removed.
With the down-scaling of integrated circuits, STI regions are increasingly used as the isolation structures. FIG. 1 illustrates a top view of an integrated circuit structure, which includes metal-oxide-semiconductor (MOS) devices 102 and 112. MOS device 102 includes gate poly 104 formed over active region 106. MOS device 112 includes gate poly 114 formed over active region 116. Active regions 106 and 116 are separated from each other and from other devices by STI regions 108, which include STI strips 1081 parallel to the gate length direction (source-to-drain direction) of MOS devices 102 and 112, and STI strips 1082 parallel to the gate width direction.
The formation of STI regions 108 is typically performed before the formation of MOS devices. During the subsequent high-temperature process steps, which may be performed at temperatures as high as about 700° C., stresses are generated due to the different coefficients of thermal expansion between STI regions 108 and active regions 106 and 116. STI regions 108 thus apply stresses to active regions 106 and 116 and adversely affect the performance of MOS devices 102 and 112. In addition, the formation of source/drain regions requires dopant implantations. In the portions of active regions 106 and 116 near STI regions 108, dopant concentrations may have fluctuations due to the diffusion of the dopants into STI regions 108.
FIG. 2 illustrates a cross-sectional view of a conventional structure. To solve the micro-loading effect, dummy polysilicon strip 120 is added over STI region 108. Dummy polysilicon strip 120 is located between polysilicon strips 104 and 114. In the source and drain regions of MOS devices 102 and 112, epitaxial regions 122 are formed by etching into substrate 124 to form recesses in substrate 124, and epitaxially growing a semiconductor material, such as silicon germanium (SiGe) in the recesses. However, since SiGe tends not to grow on STI region 108, facets 126 are formed. In addition, dummy polysilicon strip 120 has parasitic capacitance with polysilicon strips 104 and 114, both resulting in the degradation of MOS devices 102 and 112.